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hv9912 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com features switch mode controller for single switch drivers ? buck ? boost ? buck-boost and sepic works with high side current sensors closed loop control of output current high pwm dimming ratio internal 90v linear regulator (can be extended using external zener diodes) internal 2% voltage reference (0c < t a < 85c) constant frequency operationprogrammable slope compensation linear & pwm dimming +0.2a/-0.4a gate drive hiccup mode protection for both short circuit and open circuit conditions synchronization capability pin compatible with hv9911 applications led backlight applicationsgeneral led lighting applications battery powered led lamps ?? ? ? ? ? ? ? ? ? ? ? ? ?? ? general description the hv9912 is a current mode control led driver ic designed to control single switch pwm converters (buck, boost, buck-boost or sepic) in a constant frequency mode. the controller uses a peak current-mode control scheme with programmable slope compensation and includes an internal transconductance ampli?er to control the output current in closed loop enabling high output current accuracy (in the case of buck and buck-boost converters, the output current can be sensed using a high side current sensor like the hv7800). in the constant frequency mode, multiple hv9912 ics can by synchronized to each other or to an external clock using the sync pin. programmable mosfet current limit enables current limiting during input under voltage and output overload conditions. the ic also includes a 0.2a source and 0.4a sink gate driver that makes the hv9912 suitable for high power applications. an internal 90v linear regulator powers the ic eliminating the need for a separate power supply for the ic. the ic also provides a fault output, which can be used to disconnect the leds in case of a fault condition using an external disconnect fet. hv9912 also provides a ttl compatible, low-frequency pwm dimming input that can accept an external control signal with a duty ratio of 0-100% and a frequency of up to a few kilohertz. the hv9912 includes hiccup protection from both short and open circuits, with automatic recovery after the fault condition is cleared. the hv9912 is a pin compatible replacement to supertexs hv9911. it is compatible with existing hv9911 designs which have an input voltage of less than 90v by changing r ovp1 , r ovp , and r t . typical application circuit - boost switch-mode led driver ic with high current accuracy and hiccup mode protection 6 7 10 9 15 8 13 14 16 11 12 5 3 1 24 c in c dd c ref r r2 r r1 r l1 r l2 r t r slope r sc r cs r ovp1 r ovp2 c o d1 q1 l1 q2 c c r s vin vdd gnd sc rt ref clim iref sync pwmd comp fdbk fault ovp cs gate hv9912 d2 v in downloaded from: http:///
2 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 ordering information device package option 16-lead soic 9.90x3.90mm body 1.75mm height (max) 1.27mm pitch hv9912 HV9912NG-G -g indicates package is rohs compliant (green)absolute maximum ratings parameter value v in to gnd -0.5v to +100v v dd to gnd -0.3v to +13.5v cs to gnd -0.3v to (v dd + 0.3v) pwmd to gnd -0.3v to (v dd + 0.3v) gate to gnd -0.3v to (v dd + 0.3v) all other pins to gnd -0.3v to (v dd + 0.3v) continuous power dissipation (t a = +25c) 1200mw thermal impedance ( ja ) 82 o c/w junction temperature +150c storage temperature range -65c to +150c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the speci?cations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin con?guration vin vdd fdbk fault comp pwmd iref ref gnd clim cs gate ovp sc sync rt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 product marking y = last digit of year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packaging *may be part of top marking top marking bottom marking hv9912ng yww llllllll ccccccccc aaa 16-lead soic (ng) (top view) 16-lead soic (ng) electrical characteristics (the * denotes the speci?cations which apply over the full operating ambient temperature range of -4 0 o c < t a < +125 o c, otherwise the speci?cations are at t a = 25 o c. v in = 12v, unless otherwise noted.) sym parameter min typ max units conditions input v indc input dc supply voltage range * (1) - 90 v dc input voltage i insd shut-down mode supply current * - - 1.5 ma pwmd connected to gnd internal regulator v dd internally regulated voltage * 7.25 7.75 8.25 v v in = 9.0 - 90v, pwmd connected to gnd uvlo rise v dd undervoltage lockout threshold - 6.5 - 7.0 v v dd rising uvlo hyst v dd undervoltage lockout hysteresis - - 500 - mv v dd falling package may or may not include the following marks: si or downloaded from: http:///
3 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 sym parameter min typ max units conditions reference v ref ref pin voltage - 1.225 1.250 1.285 v ref bypassed with a 0.1f capacitor to gnd; i ref = 0; pwmd = gnd; 0 o c < t a < +85 o c - 1.225 1.250 1.290 ref bypassed with a 0.1f capacitor to gnd; i ref = 0; pwmd = gnd; -40 o c < t a < +125 o c v refline line regulation of reference voltage - 0 - 20 mv ref bypassed with a 0.1f capacitor to gnd; i ref = 0; v dd = 7.25 C 12v; pwmd = gnd v refload load regulation of reference voltage - 0 - 10 mv ref bypassed with a 0.1f capacitor to gnd; i ref = 0-500a; pwmd = gnd pwm dimming v pwmd(lo) pwmd input low voltage * - - 0.8 v --- v pwmd(hi) pwmd input high voltage * 2.0 - - v --- r pwmd pwmd pull-down resistance - 50 100 150 k? v pwmd = 5.0v gate i source gate short circuit current - 0.2 - - a v gate = 0v i sink gate sinking current - 0.4 - - a v gate = v dd t rise gate output rise time - - 50 85 ns c gate = 1.0nf t fall gate output fall time - - 25 45 ns c gate = 1.0nf over voltage protection v ovp, rising over voltage rising trip point - 4.75 5.00 5.25 v ovp rising v ovp, hyst over voltage hysteresis - - 0.50 - v ovp falling current sense t blank leading edge blanking - 100 - 280 ns 0 o c < t a < +85 o c - 100 - 330 -40 o c < t a < +125 o c t delay1 delay to output of c omp comparator - - - 200 ns comp = v dd ; c lim = ref; c sense = 0 to 600mv step t delay2 delay to output of c limit comparator - - - 200 ns comp = v dd ; c lim = 300mv; c sense = 0 to 400mv step v offset comparator offset voltage - -10 - 10 mv --- internal transconductance opamp gb gain bandwidth product # - 1.0 - mhz 75pf capacitance at op pin a v open loop dc gain - 60 - - db output open electrical characteristics (cont.) (the * denotes the speci?cations which apply over the full operating ambient temperature range of -4 0 o c < t a < +125 o c, otherwise the speci?cations are at t a = 25 o c. v in = 12v, unless otherwise noted.) downloaded from: http:///
4 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 notes: (1) see application information for minimum input voltage. * the speci?cations which apply over the full operating temperature range at -40 o c < t a < +125 o c are guaranteed by design and characterization. # denotes speci?cations guaranteed by design. sym parameter min typ max units conditions electrical characteristics (cont.) (over recommended operating conditions. v in = 24v, t a = 25c, unless otherwise speci?ed) v cm input common-mode range # -0.3 - 3.0 v --- v o output voltage range # 0.7 - 6.75 v --- g m transconductance - 450 550 650 a/v --- v offset input offset voltage - -5.0 - 5.0 mv --- i bias input bias current # - 0.5 1.0 na --- oscillator f osc1 oscillator frequency * 99 106 118 khz r t = 500k? f osc2 oscillator frequency * 510 580 650 khz r t = 96k? d max maximum duty cycle - 87 - 93 % --- v synch sync input high - 2.0 - - v --- v syncl sync input low - - - 0.8 v --- i outsync sync output current - - 18 - a --- output short circuit g sc gain for short circuit comparator - 1.9 2.0 2.1 v --- v omin minimum output voltage of the gain stage - 0.125 - 0.25 v 0 o c < t a < +85 o c, i ref = gnd - 0.125 - 0.26 -40 o c < t a < +125 o c, i ref = gnd t off propagation time for short circuit detection - - - 250 ns pwmd = v dd , i ref = 400ma; fdbk step from 0 to 900mv; fault goes from high to low t rise,fault fault output rise time - - - 300 ns 330pf capacitor at fault pin t fall,fault fault output fall time - - 300 ns 330pf capacitor at fault pin t blank,sc blanking time - 480 - 900 ns --- i hiccup current source at comp pin used for hiccup mode protection - 5.0 - a --- slope compensation i slope current sourced out of sc pin * 0 - 100 a --- g slope internal current mirror ratio - 1.80 2.00 2.26 - i slope = 50a ; r sc = 1.0k? downloaded from: http:///
5 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 functional block diagram v bg vin vdd ref gate fdbk iref comp gnd pwmd por rt sync s r q blanking cs sc ramp 1:2 ovpd ovp fault ss ss scd clim linear regulator + _ +_ one shot + _ hiccup/dimming block + _ por ovd scd pwmd ss 2 g m 5v rising4.5v falling pwmd 13r r 5.60/6.10v t blank t blank,sc + _ functional description power topology the hv9912 is a switch-mode converter led driver de- signed to control a continuous conduction mode buck or boost in a constant frequency (or constant off-time) mode. the ic includes an internal linear regulator, which operates from input voltages up to 90v eliminating the need for an external power supply for the ic. the ic includes features typically required in led drivers like open led protection, output short circuit protection, linear and pwm dimming, programmable input current limiting and accurate control of the led current. a high current gate drive output enables the controller to be used in high power converters. the hv9912 is an enhanced version of the hv9911 with hysteretic over-voltage protection and hiccup mode short circuit protection. the ic includes a blanking network con- trolled by the pwmd input to prevent the short circuit protec- tion from triggering prematurely during pwm dimming due to the parasitic capacitance of the led string. it also allows the iref pin to be pulled all the way down to gnd without triggering the short circuit protection. it is a pin compatible replacement to the hv9911. linear regulator the hv9912 can be powered directly from its vin pin that withstands a voltage up to 90v. when a voltage is applied at the vin pin, the hv9912 tries to maintain a constant 7.75v (typ) at the vdd pin. the regulator also has a built in under- voltage lockout which shuts off the ic if the voltage at the vdd pin falls below the uvlo threshold. downloaded from: http:///
6 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 the vdd pin must be bypassed by a low esr capacitor (0.1f) to provide a low impedance path for the high fre- quency current of the output gate driver. the input current drawn from the vin pin is a sum of the 1.5ma current drawn by the internal circuit and the current drawn by the gate driver (which in turn depends on the switch- ing frequency and the gate charge of the external fet). i in = 1.5ma + (q g x f s ) (eqn. 1) in the above equation, fs is the switching frequency and q g is the gate charge of the external fet (which can be ob- tained from the datasheet of the fet). minimum input voltage at vin pin the minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. the internal linear regulator will regulate the voltage at the vdd pin when vin is between 9v and 90v. however, when vin is less than 9v, the converter will still function as long as vdd is greater than the under voltage lockout. thus, the converter might be able to start at lower than 9v. the start/stop voltages at the vin pin can be deter- mined using the minimum voltage drop across the linear reg- ulator as a function of the current drawn. this data is shown in fig. 1 for ambient temperatures of 25oc and 85oc. assume an ambient temperature of 85 o c. assuming the ic is driving a 15nc gate charge fet at 200khz, the total input current is estimated to be 4.5ma (using eqn. 1). at this input current, the minimum voltage drop from fig. 1 can be ap- proximately estimated to be v drop = 1.25v. however, before the ic starts switching the current drawn will be 1.5ma. at this current level, the voltage drop is approximately v drop1 = 0.3v. thus, the start/stop vin voltages can be computed to be: vin start = uvlo max + v drop1 (eqn. 2) = 7.0v + 0.3v = 7.3v vin stop = uvlo max - uvlo + v drop = 7.0v - 0.5v + 1.25v = 7.75v fig. 1 headroom vs input current in this case, the gate drive draws too much current and vin start is less than vin stop . in such cases, the ic will oscil- late between on and off if the input voltage is between the start and stop voltages. in these circumstances, it is recom- mended that the input voltage be kept higher than vin stop . reference hv9912 includes a 2% accurate, 1.25v reference, which can be used as the reference for the output current as well as to set the switch current limit. the reference is buffered so that it can deliver a maximum of 500a external current to drive the external circuitry. the reference should be by- passed with at least a 10nf low esr capacitor. note: in order to avoid abnormal start-up conditions, the by- pass capacitor at the ref pin should not exceed 0.1f. oscillator connecting a resistor between r t and gnd will program the time period. in both cases, resistor r t sets the current which charges an internal oscillator capacitor. the capacitor voltage ramps up linearly and when the voltage increases beyond the internal set voltage, a comparator triggers the set input of the internal sr ?ip-?op. this starts the next switching cycle. the time period of the oscillator can be computed as: t s r t x 18pf (eqn. 3) synchronization the sync pin is an input/output (i/o) port to a fault toler- ant peer-to-peer and/or master clock synchronization circuit. for synchronization, the sync pins of multiple hv9912 based converters can be connected together and may also be connected to the open drain output of a master clock. when connected in this manner, the oscillators will lock to the device with the highest operating frequency. when syn- chronizing multiple ics, it is recommended that the same timing resistor be (corresponding to the switching frequency) be used in all the hv9912 circuits. in rare occasions, given the length of the connecting lines for the sync pins, a resistor between sync and gnd may be required to damp any ringing due to parasitic capacitances. it is recommended that the resistor chosen be greater than 300k?. when synchronized in this manner, a permanent high or low condition on the sync pin will result in a loss of syn- chronization, but the hv9912 based converters will continue to operate at their individually set operating frequency. since loss of synchronization will not result in total system failure, the sync pin is considered fault tolerant. minimum voltage drop vs. i in 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 i in (ma) minimum voltage drop (v) t a = 25 o c t a = 85 o c downloaded from: http:///
7 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 slope compensation for continuous conduction mode converters operating in the constant frequency mode, slope compensation becomes necessary to ensure stability of the peak current mode con- troller, if the operating duty cycle is greater than 0.5. choos- ing a slope compensation which is one half of the down slope of the inductor current ensures that the converter will be stable for all duty cycles. slope compensation can be programmed by two resistors r slope and r sc . assuming a down slope of ds (a/s) for the inductor current, the slope compensation resistors can be computed as: r sc = r slope x ds x 10 6 x t s x r cs (eqn. 4) 10 where r cs is the current sense resistor which senses the switching fet current. note: the maximum current that can be sourced out of the sc pin is limited to 100a. this limits the minimum value of the r slope resistor to 25k?. if the equation for slope com- pensation produces a value of r slope less than this value, then r sc would have to be reduced accordingly. it is recom- mended that r slope be chosen in the range of 25 - 50k?. current sense the current sense input of the hv9912 includes a built in 100ns (minimum) blanking time to prevent spurious turn off due to the initial current spike when the fet turns on. the hv9912 includes two high-speed comparators - one is used during normal operation and the other is used to limit the maximum input current during input under voltage or overload conditions. the ic includes an internal resistor divider network, which steps down the voltage at the comp pin by a factor of 15. this stepped-down voltage is given to one of the compara- tors as the current reference. the reference to the other comparator, which acts to limit the maximum inductor cur- rent, is given externally. it is recommended that the sense resistor r cs be chosen so as to provide about 250mv current sense signal. current limit current limit has to be set by a resistor divider from the 1.25v reference available on the ic. assuming a maximum operating inductor current i pk (including the ripple current), the maximum voltage at the clim pin can be set as: v clim 1.2 x i pk x r cs + 5 x r cs x 0.9 (eqn. 5) r slope note that this equation assumes a current limit at 120% of the maximum input current. also, if v clim is greater than 450mv, the saturation of the internal opamp will determine the limit on the input current rather than the clim pin. in such a case, the sense resistor r cs should be reduced till v clim reduces below 550mv. it is recommended that no capacitor be connected between clim and gnd. internal 1mhz transconductance ampli?er hv9912 includes a built in 1mhz transconductance ampli- ?er, with tri-state output, which can be used to close the feedback loop. the output current sense signal is connected to the fdbk pin and the current reference is connected to the iref pin. the output of the opamp is controlled by the signal applied to the pwmd pin. when pwmd is high, the output of the opamp is connected to the comp pin. when pwmd is low, the output is left open. this enables the integrating capacitor to hold the charge when the pwmd signal has turned off the gate drive. when the ic is enabled, the voltage on the inte- grating capacitor will force the converter into steady state almost instantaneously. the output of the opamp is buffered and connected to the current sense comparator using a 15:1 divider. the buffer helps to prevent the integrator capacitor from discharging during the pwm dimming state. pwm dimming pwm dimming can be achieved by driving the pwmd pin with a ttl compatible square wave source. the pwm sig- nal is connected internally to the three different nodes - the transconductance ampli?er, the flt output and the gate output. when the pwmd signal is high, the gate and flt pins are enabled and the output of the transconductance opamp is connected to the external compensation network. thus, the internal ampli?er controls the output current. when the pwmd signal goes low, the output of the transconductance ampli?er is disconnected from the compensation network. thus, the integrating capacitor maintains the voltage across it. the gate is disabled, so the converter stops switching and the flt pin goes low, turning off the disconnect switch. the output capacitor of the converter determines the pwm dimming response of the converter, since it has to get charged and discharged whenever the pwmd signal goes high or low. in the case of a buck converter, since the in- ductor current is continuous, a very small capacitor is used across the leds. this minimizes the effect of the capacitor on the pwm dimming response of the converter. however, in the case of a boost converter, the output current is dis- downloaded from: http:///
8 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 continuous and a very large output capacitor is required to reduce the ripple in the led current. thus, this capacitor will have a signi?cant impact on the pwm dimming response. by turning off the disconnect switch when pwmd goes low, the output capacitor is prevented from being discharged and thus the pwm dimming response of the boost converter is greatly improved. note that in case of continuous conduction mode boost con- verters, disconnecting the capacitor might cause a sudden spike in the capacitor voltage as the energy in the inductor is dumped into the capacitor. this increase in the capacitor voltage might cause the ovp comparator to trip if the ovp point is set too close to the maximum operating voltage. thus, either the capacitor has to be larger to absorb this energy without increasing the capacitor voltage signi?cantly or the ovp set point has to be increased. false triggering of the short circuit comparator during pwm dimming during pwm dimming, the parasitic capacitance of the led string causes a spike in the output current when the discon- nect fet is turned on. with the hv9911, this parasitic spike in the output current caused the ic to falsely detect an over current condition and shut down. to prevent this false shut- down, an r-c ?lter was used at the fdbk pin to ?lter this spike. to prevent this false triggering in the hv9912, there is a built-in 500ns blanking network for the short circuit compara- tor, which eliminates the need for the external r-c low pass ?lter. this blanking network is activated when the pwmd input goes high. thus, the short circuit comparator will not see the spike in the led current during the pwm dimming turn-on transition. once the blanking timer is completed, the short circuit comparator will start monitoring the output cur- rent. thus, the total delay time for detecting a short circuit will depend on the condition of the pwmd input. if the output short circuit exists before the pwmd signal goes high, the total detection time will be: t detect1 = t blank,sc(max) + t delay(max) 900 + 250 (eqn. 6) 1150ns(max) if the short circuit occurs when the pwmd signal is already high, the time to detect will be: t detect1 = t delay(max) 250ns(max) (eqn. 7) hiccup timer the hv9912 reuses the compensation network on the comp pin to create a timer which is activated upon startup or when a detected fault has been cleared. when a fault is detected (either open circuit or short circuit) or upon startup, the comp pin is disconnected from the g m ampli?er and the gate and flt pins are pulled low disabling the led driver. when the fault has cleared, a 5.0a current source is activated which pulls the comp network up to 5.0v. once the voltage at the comp network reaches 5.0v, the 5.0a sourcing current is disconnected and a 5.0a sinking current is activated which pulls the comp pin low. when the voltage at the comp pin reaches 1.0v, the sinking current is discon- nected and the g m ampli?er is reconnected to the comp pin. the flt pin goes high and the gate pin is now allowed to switch. the closed loop control then takes over the control of the led current. startup condition the startup waveforms are shown in fig. 2. assuming a pole-zero r-c network at the comp pin (series combination of r z and c z in parallel with c c ), the start-up delay time can be approximately computed as t delay t por + ( c c + c z ) x 9v (eqn. 8) 5a this equation assumes that the voltage drop across r z can be neglected compared to the voltage swing at the comp pin, which is true in most of the cases (r z < 100k). the por time (t por ) for the hv9912 is 10s. fig. 2 waveforms during startup v in por comp 5.0v 1.0v pull-up with 5.0a gm control flt t delay t por pull-down with 5.0a downloaded from: http:///
9 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 fault condition in the case of a fault condition (either open circuit or short circuit), the same sequence is repeated with the only differ- ence being that the comp pin voltage does not start from zero, but rather from its steady-state condition. short circuit protection when a short circuit condition is detected (output current be- comes higher than twice the steady state current), the gate and flt outputs are pulled low. as soon as the disconnect fet is turned off, the output current goes to zero and the short circuit condition disappears. at this time, the hiccup timer is started (fig. 3). once the timing is complete, the converter attempts to restart. if the fault condition still per- sists, the converter shuts down and goes through the cycle again. if the fault condition is cleared (due to a momentary output short) the converter will start regulating the output current normally. this allows the led driver to recover from accidental shorts without having to reset the ic. the hiccup time will depend on the steady state voltage of the comp pin (v comp ). this is typically in the range of 3 - 4v. the hiccup time can be approximately computed as: t hiccup (c c + c z ) x 9v - v comp (eqn. 9) 5a fig. 3 short circuit protection over voltage protection the hv9912 provides hysteretic over voltage protection allowing the ic to recover in case the led load is discon- nected momentarily. when the load is disconnected in a boost converter, the output voltage rises as the output capacitor starts charging. when the output voltage reaches the ovp rising threshold, the hv9912 detects an over voltage condition and turns off the converter. the converter is turned back on only when the output voltage falls below the falling ovp threshold (which is 10% lower than the rising threshold). this time is mostly dictated by the r-c time constant of the output capacitor co and the resistor network used to sense over voltage (r ovp1 + r ovp2 ). in case of a persistent open circuit condition, this cycle keeps repeating maintaining the output voltage within a 10% band. in most designs, the lower threshold voltage of the over volt- age protection when the converter will be turned on will be more than the led string voltage. thus, when the led load is reconnected to the output of the converter, the voltage differential between the actual output voltage and the led string voltage will cause a spike in the output current when the flt signal goes high. this causes a short circuit to be detected and the hv9912 will go into short circuit protec- tion. this behavior continues till the output voltage becomes lower than the led string voltage, at which point no fault will be detected and normal operation of the circuit will com- mence (fig. 4). the various delay times can be computed as follows: t rc 0.1 x (r ovp1 + r ovp2 ) x c o (eqn. 10) t hiccup1 (c c + c z ) x 9v - v comp (eqn. 11) 5a t hiccup2-n (c c + c z ) x 9v (eqn. 12) 5a note that the number of hiccup cycles might be more than two. output current flt comp 5.0v1.0v hiccup time t hiccup short circuit occurs normal operation resumes downloaded from: http:///
10 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 linear dimming linear dimming can be accomplished by varying the voltage at the iref pin, as the output current is proportional to the voltage at the iref pin. this can be done either by using a potentiometer from the ref pin or by applying an external voltage source at the iref pin. in the hv9911, due to the offset voltage of the short circuit comparator as well as the non-linearity of the x2 gain stage, pulling the iref pin very close to gnd will cause the internal short circuit comparator to trigger and shut down the ic. to overcome this in the hv9912, the minimum output of the gain stage is limited to 125 ~ 250mv, allowing the iref pin to be pulled all the way to 0v without triggering the short circuit comparator. note: since this control ic is a peak current mode controller, pulling the iref pin to zero will not cause the led current to become zero. the converter will still be operating at its mini- mum on-time causing a very small current to ?ow through the leds. to get zero led current, the pwmd input has to be pulled to gnd. fig. 4 open circuit protection output cap voltage flt comp 5v1v 80v 100v output current 90v led string voltage ovp on t rc t hiccup1 t hiccup2 led string reconnects ovp off led string disconnects downloaded from: http:///
11 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com hv9912 pin # pin description 1 vin this pin is the input of a 90v high voltage regulator. 2 vdd this is a power supply pin for all internal circuits. it must be bypassed with a low esr capacitor t o gnd (at least 0.1f). 3 gate this pin is the output gate driver for an external n-channel power mosfet. 4 gnd ground return for all the low power analog internal circuitry. this pin must be connected to the ret urn path from the input. 5 cs this pin is used to sense the source current of the external power fet. it includes a built-in 100ns (min) blanking time. 6 sc this pin is used to set the slope compensation. 7 rt this pin sets the frequency of the power circuit. a resistor between rt and gnd will program the circuit in constant frequency mode. 8 sync this i/o pin may be connected to the sync pin of other hv9912 circuits and will cause the oscillator s to lock to the highest frequency oscillator. 9 clim this pin provides a programmable input current limit for the converter. the current limit can be set by using a resistor divider from the ref pin. 10 ref this pin provides 2% accurate reference voltage. it must be bypassed with a 0.01 C 0.1f capacitor to gnd. 11 fault this pin is pulled to ground when there is an output short circuit condition or output over voltage condition. this pin can be used to drive an external mosfet in the case of boost converters to disconnect the load from the source. 12 ovp this pin provides the over voltage protection for the converter. when the voltage at this pin excee ds 5.0v, the gate output of the hv9912 is turned off and flt goes low. the ic will turn on when the voltage at the pin goes below 4.5v. 13 pwmd when this pin is pulled to gnd (or left open), switching of the hv9912 is disabled. when an external ttl high level is applied to it, switching will resume. 14 comp stable closed loop control can be accomplished by connecting a compensation network between comp and gnd. this capacitor also controls the hiccup time. 15 iref the voltage at this pin sets the output current level. the current reference can be set using a resi stor divider from the ref pin. 16 fdbk this pin provides output current feedback to the hv9912 by using a current sense resistor. pin description downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receive s an adequate product liability indemnification insu rance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defect ive due to workmanship. no responsibility is assume d for possible omissions and inaccuracies. circuitr y and specifications are subject to change without notice . for the latest product specifications refer to th e supertex inc. (website: http//www.supertex.com) ?2009 supertex inc. all rights reserved. unauthorized use or reproduct ion is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com 12 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the la test package outline information go to http://www.supertex.com/packaging.html .) hv9912 doc.# dsfp-hv9912 a012210 16-lead soic (narrow body) package outline (ng) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 9.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation ac, issue e, sept. 2005. * this dimension is not speci?ed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-16song, version g041309. d seating plane gauge plane l l1 l2 top view side view view a-a view b view b 1 e1 e a a2 a1 a a seating plane e b h h 16 1 note 1 note 1 (index area d/2 x e1/2) note: this chamfer feature is optional. if it is not present, then a pin 1 identi?er must be located in th e index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1. downloaded from: http:///

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